AMF-Placer
2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
Related Pages
Here is a list of all related documentation pages:
[detail level
1
2
3
]
Introduction
▼
Get Started
Build the Placer
▼
Run An Example
Runtime Log Explanation
Set the Placement Configuration in JSON file
Extract Design Information from Vivado
Extract Device Information from Vivado
Load the Output Placement in Vivado
Visualize the Placement Convergence Procedure
Customize the Placement Flow
▼
Benchmarks and Experimental Results
Benchmarks Details
▼
Experimental Results
Experimental Results of AMF-Placer 1.0
Experimental Results of AMF-Placer 2.0
▼
Download Post-Implementation Vivado Projects
Benchmarks Details
Publications
▼
Implementation Explanation
Wirelength Optimzation in Quadratic Placement Flow
Parallel Cell Spreading
Parallel Progressive Macro Legalization
Mixed-size Packing
Optimization for Timing, Clocking and Congestion
Runtime Log Explanation
Existing Problems When Exporting To Vivado
Some Failure Lessons
Generated by
1.8.18