Experimental Results

AMF-Placer 2.0 is the extension of AMF-Placer 1.0. AMF-Placer 1.0 is a wirelength-driven mixed-size FPGA placer equipped with a series of new techniques for wirelength optimization, cell spreading, packing, and legalization. Experimental results indicate that AMF-Placer 1.0 can improve HPWL by 20.4%-89.3% and reduce runtime by 8.0%-84.2%, compared to the baseline. Furthermore, utilizing the parallelism of the proposed algorithms, with 8 threads, the placement procedure can be accelerated by 2.41x on average. Experimental results can be found in this page (Experimental Results of AMF-Placer 1.0).

Standing upon the shoulders of AMF-Placer 1.0, AMF-Placer 2.0 is equipped with a series of new techniques for timing optimization, including an effective regression-based timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Experimental results can be found in this page (Experimental Results of AMF-Placer 2.0).