AMF-Placer
2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
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Here, we will provide the details of the benchmarks, including related papers, their overall parameters, and corresponding post-implementation Vivado projects. Besides, we try to evaluate our propsoed optimization techiniques via comprehensive comparison and provide the runtime log files of related paper for researchers who are interested in our work:
After our placer extension for timing and specific designs is ready, more benchmarks and results will be provided.