AMF-Placer  2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
Get Started

Here, we will go through some basic steps for users to build the placer and run a placement flow for a new design/device with a new placement configuration:

  1. Build the Placer
  2. Run An Example
  3. Set the Placement Configuration in JSON file
  4. Extract Design Information from Vivado
  5. Extract Device Information from Vivado
  6. (Optional) Load the Output Placement in Vivado
  7. (Optional) Visualize the Placement Convergence Procedure
  8. (Optional) Customize the Placement Flow