We were trapped by many problems during our implementation of the placer and experiments. We hope people in this area will not encounter those situations in the future so we list some lessons we learnt.

1. For the physical syhthesis, at the beginning, involving visualization can be very helpful to locate the problems and figure out what's going on with your algorithms. DO consider include this part in your development procedure.
2. All the changes/optimization in the convergence flow of physical synthesis should be progressive. Sudden changes of system parameters/option will cause many problems.
3. When you get significant improvement for a benchmark case, keep calm and test all the benchmarks before further improvement of the framework because some optimization techniques might be sensitive to the benchmark characteristics.
4. Double check when some operations are conducted for specific types of elements, for example, some cell types will have significant impact on the others.
5. Analytical model cannot improve or model everything because of the device complexity so sometimes you may give a chance to heuristic solutions.
6. When trying to adopt the existing solutions into your flow, the implict assumptions/requirements of those solutions should be clearly considered.
7. We might need a global data structure to store all the hyperparameters for better control of the entire placement flow since now, many parameters are scattered in difference class, making it hard to analyze the correlation between them for 3rd party users.
8. AMF-Placer 2.0 is the first FPGA placer that can handle the timing-driven mixed-size placement of practical complex designs with various FPGA resources and achieves comparable quality compared to the latest commercial tools. However, according to the analysis of the concrete placement, we find that the major existing limitations of AMF-Placer 2.0 can be categorized into to three types, listed as follows: (1) Timing estimation accuracy: The timing estimation model is relatively optimistic without considering a few of congested regions overlapped with the critical paths. This problem is noticeable for benchmark DigitRecog and MemN2N, which might be resolved by machine-learning-based timing estimation in the future. Moreover, the timing analysis and optimization at the floorplanning stage might be insufficient, which leads to a bad starting point for the later placement flow. Besides, a noticeable proportion of the WNS for benchmark DigitRecog is caused by clock skew, which is not considered by AMF-Placer 2.0 as well as the other existing works for the Ultrascale FPGA architecture; (2) Design-aware factors: The design netlists for Vivado placement are actually hierarchical. According to the placement results of Vivado, based on the design hierarchy information, regularity can be fully utilized for the placement of local circuits, e.g., parallel accumulator datapaths, buses, and FIFOs. However, AMF-Pacer 2.0 consumes a flattened netlist, missing the opportunities of regularity-related optimization. These problems are considered during the currect development of AMF-Placer.