AMF-Placer
2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
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26 #ifndef _INITIALPACKER
27 #define _INITIALPACKER
62 std::map<std::string, std::string> &
JSONCfg)
91 std::vector<DesignInfo::DesignCell *>
95 bool exactMatch =
false);
104 void setDSPRegs(std::vector<DesignInfo::DesignCell *> &DSPTailsToBeCheckedRegisterAttr);
128 std::vector<DesignInfo::DesignCell *>
checkCompatibleFFs(std::vector<DesignInfo::DesignCell *> FFs);
205 :
CSId(curFF->getControlSetInfo()->getId()),
CLK(curFF->getControlSetInfo()->
getCLK()),
206 SR(curFF->getControlSetInfo()->
getSR()),
CE(curFF->getControlSetInfo()->getCE())
209 FFs.push_back(curFF);
215 assert(anotherControlSet.
getSize() > 0 &&
"the other one control set should not be empty.");
223 assert(anotherControlSet.
getSize() > 0 &&
"the other one control set should not be empty.");
236 inline const std::vector<DesignInfo::DesignCell *> &
getFFs()
const
261 FFs.push_back(curFF);
271 for (
unsigned int i = 0;
i <
FFs.size();
i++)
306 std::vector<DesignInfo::DesignCell *>
FFs;
319 for (
int i = 0;
i < 2;
i++)
322 for (
int j = 0; j < 2; j++)
325 for (
int k = 0; k < 4; k++)
327 LUTs[
i][j][k] =
nullptr;
328 FFs[
i][j][k] =
nullptr;
339 {{
nullptr,
nullptr,
nullptr,
nullptr}, {
nullptr,
nullptr,
nullptr,
nullptr}},
340 {{
nullptr,
nullptr,
nullptr,
nullptr},
341 {
nullptr,
nullptr,
nullptr,
nullptr}}};
343 {{
nullptr,
nullptr,
nullptr,
nullptr}, {
nullptr,
nullptr,
nullptr,
nullptr}},
344 {{
nullptr,
nullptr,
nullptr,
nullptr},
345 {
nullptr,
nullptr,
nullptr,
nullptr}}};
368 float CARRYChainSiteOffset);
void dumpMacroHighLight()
std::map< std::string, std::string > & JSONCfg
InitialPacker will identify macros from the design netlist based on pattern matching.
std::map< int, PlacementInfo::PlacementUnit * > & cellId2PlacementUnit
unsigned int getSize() const
int findFF(DesignInfo::DesignCell *curFF)
PlacementInfo * placementInfo
std::vector< PlacementInfo::PlacementMacro * > & placementMacros
void loadOtherCLBMacros(std::string RAMMacroListFromVivadoFileName)
load the special macros from the design file. vendors might allow users to specify some primitive mac...
a fixed group of multiple standard cells with constraints of their relative locations
PlacementInfo::CompatiblePlacementTable * compatiblePlacementTable
a DesignCell in design netlist, DesignPin objects of which might connect to DesignNet objects
void loadFixedPlacementUnits(std::string fixedPlacementUnitsFromVivadoFileName)
load the fixed elements (e.g., IOs) from the design file.
DesignInfo::DesignNet * SR
a design net (hyperedge) defined in the design, connecting to pins of cells
DesignInfo::DesignCell * Carry
DesignInfo::DesignCell * MuxF8[2]
DesignInfo::DesignNet * getCE() const
void findDSPMacros()
detects DSP macros and clusters the related cells into PlacementInfo::PlacementMacro
PackedControlSet & operator=(const PackedControlSet &anotherControlSet)
std::vector< PlacementInfo::PlacementUnit * > & placementUnits
DesignInfo::DesignNet * CE
std::vector< DesignInfo::DesignCell * > checkCompatibleFFs(std::vector< DesignInfo::DesignCell * > FFs)
check the control set of the candidate FFs and select the control set with the most FFs to be packed ...
This header file contains the classes of data for a standalone design netlist.
DesignInfo::DesignNet * getCLK() const
DesignInfo::DesignCell * MuxF7[2][2]
This header file contains the classes of data for a standalone device.
void findLUTRAMMacros()
detects LUTRAM macros and clusters the related cells into PlacementInfo::PlacementMacro
DesignInfo::DesignNet * getSR()
PackedControlSet(const PackedControlSet &anotherControlSet)
DesignInfo::DesignCell * LUTs[2][2][4]
std::vector< PlacementInfo::PlacementUnit * > & cellId2PlacementUnitVec
PackedControlSet(DesignInfo::DesignCell *curFF)
DesignInfo::DesignNet * getSR() const
void setDSPRegs(std::vector< DesignInfo::DesignCell * > &DSPTailsToBeCheckedRegisterAttr)
std::set< DesignInfo::DesignCell * > & cellInMacros
std::vector< PlacementInfo::PlacementUnit * > & fixedPlacementUnits
describes the type mapping from design to device, where a cell can be placed (which BEL in which site...
const std::vector< DesignInfo::DesignCell * > & getFFs() const
void pack()
extract the macros from the netlist to construction PlacmentMacro
DesignInfo::DesignNet * getCLK()
void findUnpackedUnits()
other non-Macro elements will be instantiated as PlacementInfo::PlacementUnpackedCell
void LUTFFPairing()
directly pack some LUTs/FFs if the LUT has only one fan-out.
void findMuxMacros()
detects Mux macros and clusters the related cells into PlacementInfo::PlacementMacro
ControlSetInfo * getControlSetInfo()
Get the Control Set Info object of this cell.
InitialPacker(DesignInfo *designInfo, DeviceInfo *deviceInfo, PlacementInfo *placementInfo, std::map< std::string, std::string > &JSONCfg)
Construct a new Initial Packer object.
std::vector< DesignInfo::DesignCell * > FFs
std::vector< DesignInfo::DesignCell * > BFSExpandViaSpecifiedPorts(std::string portPattern, DesignInfo::DesignCell *startCell, bool exactMatch=false)
BFS to find the core cells of a macro based on some pre-defined patterns of cascaded cells.
std::vector< PlacementInfo::PlacementUnpackedCell * > & placementUnpackedCells
void mapCarryRelatedRouteThru(PlacementInfo::PlacementMacro *CARRYChain, DesignInfo::DesignCell *coreCell, float CARRYChainSiteOffset)
Information class related to FPGA device, including the details of BEL/Site/Tile/ClockRegion.
SiteBELMapping is a contain recording the mapping between cells and BELs.
control set information container used during initial packing.
const int getId() const
Get the Id of the control set (each control set will have a unique Id)
DesignInfo::DesignCell * FFs[2][2][4]
This header file mainly contains the definition of class PlacementInfo, including information related...
void addFF(DesignInfo::DesignCell *curFF)
void enhanceIONets()
enhance the nets connected to the IO ports
Information related to FPGA designs, including design cells and their interconnections.
DesignInfo::DesignNet * CLK
void findBRAMMacros()
detects BRAM macros and clusters the related cells into PlacementInfo::PlacementMacro
Information related to FPGA placement (wirelength optimization, cell spreading, legalization,...
void findCARRYMacros()
detects CARRY macros and clusters the related cells into PlacementInfo::PlacementMacro