DesignInfo.h

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#ifndef _DESIGNINFO
#define _DESIGNINFO
 
#include "DeviceInfo.h"
#include <assert.h>
#include <fstream>
#include <iostream>
#include <map>
#include <sstream>
#include <string>
#include <vector>
 
#define CELLTYPESTRS                                                                                                   \
    "LUT1", "LUT2", "LUT3", "LUT4", "LUT5", "LUT6", "LUT6_2", "FDCE", "FDPE", "FDRE", "FDSE", "LDCE", "AND2B1L",       \
        "CARRY8", "DSP48E2", "MUXF7", "MUXF8", "SRL16E", "SRLC32E", "RAM32M16", "RAM64M", "RAM64X1D", "RAM32M",        \
        "RAM32X1D", "RAM32X1S", "RAM64X1S", "RAM64M8", "RAM256X1D", "FIFO36E2", "FIFO18E2", "RAMB18E2", "RAMB36E2",    \
        "BUFGCE", "BUFG_GT", "BUFG_GT_SYNC", "BUFGCE_DIV", "BUFGCTRL", "GTHE3_CHANNEL", "GTHE3_COMMON", "IOBUF",       \
        "IBUF", "IBUFDS", "IOBUFDS", "IBUFDS_GTE3", "IBUF_ANALOG", "IOBUFE3", "MMCME3_ADV", "OBUF", "OBUFT",           \
        "PCIE_3_1", "BSCANE2", "SYSMONE1", "RXTX_BITSLICE", "BITSLICE_CONTROL", "TX_BITSLICE_TRI", "OSERDESE3",        \
        "RIU_OR", "PLLE3_ADV", "HPIO_VREF", "OBUFDS_DUAL_BUF"
 
class DesignInfo
{
  public:
    enum DesignElementType
    {
        ElementType_cell = 0,
        ElementType_pin,
        ElementType_net,
        ElementType_graph
    };
 
    enum DesignCellType // have to have the the same order with CELLTYPESTRS macro
    {
        CellType_LUT1 = 0,
        CellType_LUT2,
        CellType_LUT3,
        CellType_LUT4,
        CellType_LUT5,
        CellType_LUT6,
        CellType_LUT6_2, // these are LUTs
 
        CellType_FDCE,
        CellType_FDPE,
        CellType_FDRE,
        CellType_FDSE,
        CellType_LDCE,
        CellType_AND2B1L, // these are FFs
 
        CellType_CARRY8,
        CellType_DSP48E2,
 
        CellType_MUXF7,
        CellType_MUXF8,
 
        CellType_SRL16E,
        CellType_SRLC32E, // these are shifters
 
        CellType_RAM32M16,
        CellType_RAM64M,
        CellType_RAM64X1D,
        CellType_RAM32M,
        CellType_RAM32X1D,
        CellType_RAM32X1S,
        CellType_RAM64X1S,
        CellType_RAM64M8,
        CellType_RAM256X1D, // these are LUTRAMs
 
        CellType_FIFO36E2,
        CellType_FIFO18E2,
        CellType_RAMB18E2,
        CellType_RAMB36E2, // these are BRAMs
 
        CellType_BUFGCE,
        CellType_BUFG_GT,
        CellType_BUFG_GT_SYNC,
        CellType_BUFGCE_DIV,
        CellType_BUFGCTRL, // clock-related types
 
        CellType_GTHE3_CHANNEL,
        CellType_GTHE3_COMMON,
        CellType_IOBUF,
        CellType_IBUF,
        CellType_IBUFDS,
        CellType_IOBUFDS,
        CellType_IBUFDS_GTE3,
        CellType_IBUF_ANALOG,
        CellType_IOBUFE3,
 
        CellType_MMCME3_ADV,
 
        CellType_OBUF,
        CellType_OBUFT,
        CellType_PCIE_3_1,
 
        CellType_BSCANE2,
        CellType_SYSMONE1,
        CellType_RXTX_BITSLICE,
        CellType_BITSLICE_CONTROL,
        CellType_TX_BITSLICE_TRI,
        CellType_OSERDESE3,
 
        CellType_RIU_OR,
        CellType_PLLE3_ADV,
        CellType_HPIO_VREF,
        CellType_OBUFDS_DUAL_BUF
    };
 
    inline static bool FFSRCompatible(DesignCellType typeA, DesignCellType typeB)
    {
        // CellType_FDCE,
        // CellType_FDPE,
        // CellType_FDRE,
        // CellType_FDSE,
        // CellType_LDCE,
        // CellType_AND2B1L, // these are FFs
        int AClass = -1;
        if (typeA == CellType_FDCE || typeA == CellType_FDPE)
            AClass = 0;
        else if (typeA == CellType_FDRE || typeA == CellType_FDSE)
            AClass = 1;
        else if (typeA == CellType_LDCE)
            AClass = 2;
        else if (typeA == CellType_AND2B1L)
            AClass = 3;
        assert(AClass != -1);
        int BClass = -1;
        if (typeB == CellType_FDCE || typeB == CellType_FDPE)
            BClass = 0;
        else if (typeB == CellType_FDRE || typeB == CellType_FDSE)
            BClass = 1;
        else if (typeB == CellType_LDCE)
            BClass = 2;
        else if (typeB == CellType_AND2B1L)
            BClass = 3;
        assert(BClass != -1);
        return AClass == BClass;
    }
 
    inline static bool getFFSRType(DesignCellType typeA)
    {
        int AClass = -1;
        if (typeA == CellType_FDCE || typeA == CellType_FDPE)
            AClass = 0;
        else if (typeA == CellType_FDRE || typeA == CellType_FDSE)
            AClass = 1;
        else if (typeA == CellType_LDCE)
            AClass = 2;
        else if (typeA == CellType_AND2B1L)
            AClass = 3;
        assert(AClass != -1);
        return AClass;
    }
 
    std::vector<std::string> DesignCellTypeStr{CELLTYPESTRS};
 
    enum DesignPinType
    {
        PinType_LUTInput = 0,
        PinType_LUTOutput,
        PinType_CLK, // FF clk
        PinType_Q,
        PinType_D,
        PinType_E,  // FF enable
        PinType_SR, // FF reset/set
        PinType_Others
    };
 
    class DesignElement
    {
      public:
        DesignElement(const std::string &name, DesignElement *parentPtr, DesignElementType type, int id)
            : name(name), parentPtr(parentPtr), type(type), id(id)
        {
        }
 
        DesignElement(const std::string &name, DesignElementType type, int id)
            : name(name), parentPtr(nullptr), type(type), id(id)
        {
        }
        DesignElement(bool isVirtual, DesignElementType type, int id) : parentPtr(nullptr), type(type), id(id)
        {
            assert(isVirtual);
            name = std::to_string(id);
        }
 
        DesignElement(bool isVirtual, const std::string &_name, DesignElementType type, int id)
            : parentPtr(nullptr), type(type), id(id)
        {
            assert(isVirtual);
            name = _name + "(" + std::to_string(id) + ")";
        }
 
        virtual ~DesignElement()
        {
        }
 
        inline const std::string &getName() const
        {
            return name;
        }
        inline DesignElement *getParentPtr()
        {
            return parentPtr;
        }
        inline DesignElementType getElementType()
        {
            return type;
        }
        inline int getElementIdInType()
        {
            return id;
        }
 
      private:
        std::string name;
        DesignElement *parentPtr = nullptr;
        DesignElementType type;
        int id;
    };
 
    class DesignPin;
    class DesignNet;
    class DesignCell;
    class ControlSetInfo;
 
    class DesignPin : public DesignElement
    {
      public:
        DesignPin(std::string &name, std::string &refpinname, DesignPinType pinType, bool inputOrNot,
                  DesignElement *parentPtr, int id)
            : DesignElement(name, parentPtr, ElementType_pin, id), pinType(pinType), refpinname(refpinname),
              inputOrNot(inputOrNot)
        {
        }
 
        ~DesignPin()
        {
        }
 
        static DesignPinType checkPinType(DesignCell *cell, std::string &refpinname, bool isInput);
 
        inline DesignPinType getPinType()
        {
            return pinType;
        }
 
        inline std::string &getNetName()
        {
            return netName;
        }
 
        inline void connectToNetName(std::string &_netName)
        {
            netName = _netName;
        }
 
        inline int getAliasNetId()
        {
            return aliasNetId;
        }
 
        inline void setAliasNetId(int _aliasNetId)
        {
            aliasNetId = _aliasNetId;
        }
 
        inline void connectToNetVariable(DesignNet *_netPtr)
        {
            netPtr = _netPtr;
        }
 
        inline bool isOutputPort()
        {
            return !inputOrNot;
        }
 
        inline bool isInputPort()
        {
            return inputOrNot;
        }
 
        inline void setDriverPinName(std::string &_driverPinName)
        {
            driverPinName = _driverPinName;
        }
 
        inline void setDriverPin(DesignPin *_driverPinPtr)
        {
            driverPin = _driverPinPtr;
        }
 
        inline DesignPin *getDriverPin()
        {
            return driverPin;
        }
 
        void updateParentCellNetInfo();
        inline DesignNet *getNet()
        {
            return netPtr;
        };
 
        inline DesignCell *getCell()
        {
            DesignElement *tmpElement = getParentPtr();
            DesignCell *parentCell = dynamic_cast<DesignCell *>(tmpElement);
            assert(parentCell);
            return parentCell;
        }
 
        std::string &getRefPinName()
        {
            return refpinname;
        }
 
        inline void setUnconnected()
        {
            unconnected = true;
        }
 
        inline bool isUnconnected()
        {
            return unconnected;
        }
 
        inline void setOffsetInCell(float x, float y)
        {
            offsetXInCell = x;
            offsetYInCell = y;
        }
 
        inline float getOffsetXInCell()
        {
            return offsetXInCell;
        }
 
        inline float getOffsetYInCell()
        {
            return offsetYInCell;
        }
 
        inline bool isFixed()
        {
            return fixed;
        }
 
        inline void setFixed()
        {
            fixed = true;
        }
 
      private:
        DesignPinType pinType;
        std::string netName;
        std::string refpinname;
        DesignNet *netPtr = nullptr;
        bool inputOrNot;
        bool unconnected = false;
        bool fixed = false;
        std::string driverPinName;
        DesignPin *driverPin = nullptr;
        float offsetXInCell = 0.0;
        float offsetYInCell = 0.0;
        int aliasNetId = -1;
    };
 
    class DesignNet : public DesignElement
    {
      public:
        DesignNet(std::string &name, int id, bool virtualNet = false)
            : DesignElement(name, ElementType_net, id), virtualNet(virtualNet)
        {
            if (name == "<const0>" || name == "<const1>")
            {
                isPowerNet = true;
            }
            overallClusterEnhanceRatio = 1.0;
            overallTimingEnhanceRatio = 1.0;
        }
 
        ~DesignNet()
        {
        }
 
        void connectToPinName(const std::string &_pinName);
        void connectToPinVariable(DesignPin *_pinPtr);
 
        inline std::vector<DesignPin *> &getDriverPins()
        {
            return driverPinPtrs;
        }
 
        inline std::vector<DesignPin *> &getPinsBeDriven()
        {
            return BeDrivenPinPtrs;
        }
 
        inline std::vector<DesignPin *> &getPins()
        {
            return pinPtrs;
        }
 
        inline bool isVirtual()
        {
            return virtualNet;
        }
 
        inline void enhance(int pinIdInNetA, int pinIdInNetB, float ratio)
        {
            std::pair<int, int> tmpPair(pinIdInNetA, pinIdInNetB);
            if (pinIdPinIdInNet2EnhanceRatio.find(tmpPair) == pinIdPinIdInNet2EnhanceRatio.end())
            {
                pinIdPinIdInNet2EnhanceRatio[tmpPair] = ratio;
            }
            else
            {
                pinIdPinIdInNet2EnhanceRatio[tmpPair] *= ratio;
            }
        }
 
        inline float getPinPairEnhanceRatio(int pinIdInNetA, int pinIdInNetB)
        {
            std::pair<int, int> tmpPair(pinIdInNetA, pinIdInNetB);
            if (pinIdPinIdInNet2EnhanceRatio.find(tmpPair) == pinIdPinIdInNet2EnhanceRatio.end())
            {
                return 1.0;
            }
            else
            {
                return pinIdPinIdInNet2EnhanceRatio[tmpPair];
            }
        }
 
        inline float getOverallClusterEnhanceRatio()
        {
            return overallClusterEnhanceRatio;
        }
 
        inline float getOverallTimingEnhanceRatio()
        {
            return overallTimingEnhanceRatio;
        }
 
        inline float getOverallEnhanceRatio()
        {
            return overallClusterEnhanceRatio * overallTimingEnhanceRatio;
        }
 
        inline void setOverallClusterNetEnhancement(float r)
        {
            overallClusterEnhanceRatio = r;
        }
 
        inline void setOverallTimingNetEnhancement(float r)
        {
            overallTimingEnhanceRatio = r;
        }
 
        inline void enhanceOverallClusterNetEnhancement(float r)
        {
            overallClusterEnhanceRatio *= r;
        }
 
        inline void enhanceOverallTimingNetEnhancement(float r)
        {
            overallTimingEnhanceRatio *= r;
        }
 
        inline void resetEnhanceRatio()
        {
            pinIdPinIdInNet2EnhanceRatio.clear();
            overallClusterEnhanceRatio = 1;
            overallTimingEnhanceRatio = 1;
        }
 
        inline void setGlobalClock()
        {
            isGlobalClock = true;
        }
 
        inline bool checkIsGlobalClock()
        {
            return isGlobalClock;
        }
 
        inline bool checkIsPowerNet()
        {
            return isPowerNet;
        }
 
        inline bool checkContainFixedPins()
        {
            return containFixedPins;
        }
 
        inline void setContainFixedPins()
        {
            containFixedPins = true;
        }
 
      private:
        std::vector<std::string> pinNames;
        std::vector<DesignPin *> pinPtrs;
        std::vector<DesignPin *> driverPinPtrs;
        std::vector<DesignPin *> BeDrivenPinPtrs;
        bool containFixedPins = false;
        std::map<std::pair<int, int>, float> pinIdPinIdInNet2EnhanceRatio;
        float overallClusterEnhanceRatio = 1.0;
        float overallTimingEnhanceRatio = 1.0;
        bool virtualNet;
        bool isGlobalClock = false;
        bool isPowerNet = false;
    };
 
    class DesignCell : public DesignElement
    {
      public:
        DesignCell(const std::string &name, DesignElement *parentPtr, DesignCellType cellType, int id)
            : DesignElement(name, parentPtr, ElementType_cell, id), cellType(cellType)
        {
            pinPtrs.clear();
            inputPinPtrs.clear();
            outputPinPtrs.clear();
            pinNames.clear();
            netPtrs.clear();
            inputNetPtrs.clear();
            outputNetPtrs.clear();
            netNames.clear();
        }
 
        DesignCell(const std::string &name, DesignCellType cellType, int id)
            : DesignElement(name, ElementType_cell, id), cellType(cellType)
        {
            oriCellType = cellType;
            pinPtrs.clear();
            inputPinPtrs.clear();
            outputPinPtrs.clear();
            pinNames.clear();
            netPtrs.clear();
            inputNetPtrs.clear();
            outputNetPtrs.clear();
            netNames.clear();
        }
 
        DesignCell(bool isVirtual, DesignCellType cellType, int id)
            : DesignElement(isVirtual, ElementType_cell, id), cellType(cellType), isVirtual(isVirtual)
        {
            oriCellType = cellType;
            pinPtrs.clear();
            inputPinPtrs.clear();
            outputPinPtrs.clear();
            pinNames.clear();
            netPtrs.clear();
            inputNetPtrs.clear();
            outputNetPtrs.clear();
            netNames.clear();
            assert(isVirtual);
        }
 
        DesignCell(bool isVirtual, const std::string &name, DesignCellType cellType, int id)
            : DesignElement(isVirtual, name, ElementType_cell, id), cellType(cellType), isVirtual(isVirtual)
        {
            oriCellType = cellType;
            pinPtrs.clear();
            inputPinPtrs.clear();
            outputPinPtrs.clear();
            pinNames.clear();
            netPtrs.clear();
            inputNetPtrs.clear();
            outputNetPtrs.clear();
            netNames.clear();
            assert(isVirtual);
        }
 
        ~DesignCell()
        {
            for (auto pin : pinPtrs)
                delete pin;
        }
 
        inline DesignCellType getCellType()
        {
            return cellType;
        }
 
        void addPin(DesignPin *_pinPtr);
 
        inline std::vector<DesignPin *> &getPins()
        {
            return pinPtrs;
        }
 
        void addNetForPin(DesignPin *_pinPtr, DesignNet *_netPtr);
 
        inline std::vector<DesignNet *> &getOutputNets()
        {
            return outputNetPtrs;
        }
        inline std::vector<DesignNet *> &getInputNets()
        {
            return inputNetPtrs;
        }
        inline std::vector<DesignPin *> &getOutputPins()
        {
            return outputPinPtrs;
        }
        inline std::vector<DesignPin *> &getInputPins()
        {
            return inputPinPtrs;
        }
 
        inline bool isLUT6()
        {
            return cellType == CellType_LUT6 || cellType == CellType_LUT6_2;
        }
        inline bool isLUT()
        {
            return cellType == CellType_LUT6_2 || cellType == CellType_LUT6 || cellType == CellType_LUT5 ||
                   cellType == CellType_LUT4 || cellType == CellType_LUT3 || cellType == CellType_LUT2 ||
                   cellType == CellType_LUT1;
        }
        inline bool isFF()
        {
            return cellType == CellType_FDCE || cellType == CellType_FDPE || cellType == CellType_FDSE ||
                   cellType == CellType_LDCE || cellType == CellType_FDRE || cellType == CellType_AND2B1L;
        }
        inline bool isLUTRAM()
        {
            return (cellType == CellType_RAM32M16 || cellType == CellType_RAM32X1D || cellType == CellType_RAM64X1S ||
                    cellType == CellType_RAM64M || cellType == CellType_RAM64X1D || cellType == CellType_RAM32M ||
                    cellType == CellType_RAM32X1D || cellType == CellType_RAM32X1S || cellType == CellType_RAM64X1S ||
                    cellType == CellType_RAM64M8 || cellType == CellType_RAM256X1D);
        }
        inline bool originallyIsLUTRAM()
        {
            return (oriCellType == CellType_RAM32M16 || oriCellType == CellType_RAM32X1D ||
                    oriCellType == CellType_RAM64X1S || oriCellType == CellType_RAM64M ||
                    oriCellType == CellType_RAM64X1D || oriCellType == CellType_RAM32M ||
                    oriCellType == CellType_RAM32X1D || oriCellType == CellType_RAM32X1S ||
                    oriCellType == CellType_RAM64X1S || oriCellType == CellType_RAM64M8 ||
                    oriCellType == CellType_RAM256X1D);
        }
        inline bool isBRAM()
        {
            return cellType == CellType_RAMB18E2 || cellType == CellType_RAMB36E2 || cellType == CellType_FIFO18E2 ||
                   cellType == CellType_FIFO36E2;
        }
        inline bool isMux()
        {
            return cellType == CellType_MUXF7 || cellType == CellType_MUXF8;
        }
        inline bool isCarry()
        {
            return cellType == CellType_CARRY8;
        }
        inline bool isShift()
        {
            return cellType == CellType_SRL16E || cellType == CellType_SRLC32E;
        }
        inline bool isDSP()
        {
            return cellType == CellType_DSP48E2;
        }
        inline bool checkHasDSPReg()
        {
            return hasDSPReg;
        }
        inline bool isIO()
        {
            return cellType == CellType_GTHE3_CHANNEL || cellType == CellType_GTHE3_COMMON ||
                   cellType == CellType_IOBUF || cellType == CellType_IBUF || cellType == CellType_IBUFDS ||
                   cellType == CellType_IOBUFDS || cellType == CellType_IBUFDS_GTE3 ||
                   cellType == CellType_IBUF_ANALOG || cellType == CellType_IOBUFE3 ||
 
                   cellType == CellType_MMCME3_ADV ||
 
                   cellType == CellType_OBUF || cellType == CellType_OBUFT || cellType == CellType_PCIE_3_1 ||
 
                   cellType == CellType_BSCANE2 || cellType == CellType_SYSMONE1 ||
                   cellType == CellType_RXTX_BITSLICE || cellType == CellType_BITSLICE_CONTROL ||
                   cellType == CellType_TX_BITSLICE_TRI || cellType == CellType_OSERDESE3 ||
 
                   cellType == CellType_RIU_OR || cellType == CellType_PLLE3_ADV || cellType == CellType_HPIO_VREF ||
                   cellType == CellType_OBUFDS_DUAL_BUF;
        }
 
        inline bool isClockBuffer()
        {
            return cellType == CellType_BUFGCE || cellType == CellType_BUFG_GT || cellType == CellType_BUFG_GT_SYNC ||
                   cellType == CellType_BUFGCE_DIV || cellType == CellType_BUFGCTRL;
        }
 
        inline bool isShifter()
        {
            return cellType == CellType_SRL16E || cellType == CellType_SRLC32E;
        }
 
        inline bool isTimingEndPoint()
        {
            return (isFF() || isLUTRAM() || originallyIsLUTRAM() || isBRAM() || isDSP() || isIO() || isClockBuffer() ||
                    isShifter());
        }
 
        inline bool isLogicRelated()
        {
            return (isLUT() || isFF() || isLUTRAM() || originallyIsLUTRAM() || isBRAM() || isDSP() || isShifter());
        }
 
        inline int getCellId()
        {
            return getElementIdInType();
        }
 
        inline bool isVirtualCell()
        {
            return isVirtual;
        }
 
        inline ControlSetInfo *getControlSetInfo()
        {
            return controlSetInfo;
        }
 
        inline void setControlSetInfo(ControlSetInfo *_controlSetInfo)
        {
            controlSetInfo = _controlSetInfo;
        }
 
        inline void setVirtualType(DesignCellType NewCellType)
        {
            cellType = NewCellType;
        }
 
        inline DesignCellType getOriCellType()
        {
            return oriCellType;
        }
 
        inline void addClockNet(DesignNet *aClockNet)
        {
            clockNetPtrs.insert(aClockNet);
        }
 
        inline std::set<DesignNet *> &getClockNets()
        {
            return clockNetPtrs;
        }
 
        inline void setHasDSPReg(bool _hasDSPReg)
        {
            hasDSPReg = _hasDSPReg;
        }
 
        inline void setTimingLength(int _timingLength)
        {
            timingLength = _timingLength;
        }
 
        inline int getTimingLength()
        {
            return timingLength;
        }
 
      private:
        std::vector<DesignPin *> pinPtrs;
        std::vector<DesignPin *> inputPinPtrs;
        std::vector<DesignPin *> outputPinPtrs;
        std::vector<std::string> pinNames;
        std::vector<DesignNet *> netPtrs;
        std::vector<DesignNet *> inputNetPtrs;
        std::vector<DesignNet *> outputNetPtrs;
        std::set<DesignNet *> clockNetPtrs;
        std::vector<std::string> netNames;
        DesignCellType cellType;
        DesignCellType oriCellType;
        bool isVirtual = false;
        bool hasDSPReg = false;
        ControlSetInfo *controlSetInfo = nullptr;
        int timingLength = 0;
    };
 
    class ControlSetInfo
    {
      public:
        ControlSetInfo(DesignInfo::DesignCell *curFF, int id) : id(id)
        {
            FFs.clear();
            setControlSetInfoAs(curFF);
        };
 
        ~ControlSetInfo(){};
 
        inline bool compatibleWith(DesignInfo::DesignCell *curFF)
        {
            for (auto inputPin : curFF->getInputPins())
            {
                if (inputPin->getPinType() == DesignInfo::PinType_CLK)
                {
                    if (inputPin->isUnconnected() && CLK)
                        return false;
                    if (inputPin->getNet() != CLK)
                        return false;
                }
                else if (inputPin->getPinType() == DesignInfo::PinType_E)
                {
                    if (inputPin->isUnconnected() && CE)
                        return false;
                    if (inputPin->getNet() != CE)
                        return false;
                }
                else if (inputPin->getPinType() == DesignInfo::PinType_SR)
                {
                    if (inputPin->isUnconnected() && SR)
                        return false;
                    if (inputPin->getNet() != SR)
                        return false;
                }
                else if (inputPin->getPinType() == DesignInfo::PinType_D)
                {
                    // bypass
                }
                else
                {
                    assert(false && "undefined FF input pin type.");
                }
            }
            if (FFSRCompatible(curFF->getOriCellType(), FFType))
                return false;
            return true;
        }
 
        inline void setControlSetInfoAs(DesignInfo::DesignCell *curFF)
        {
            for (auto inputPin : curFF->getInputPins())
            {
                if (inputPin->getPinType() == DesignInfo::PinType_CLK)
                {
                    if (inputPin->isUnconnected())
                        CLK = nullptr;
                    CLK = inputPin->getNet();
                }
                else if (inputPin->getPinType() == DesignInfo::PinType_E)
                {
                    if (inputPin->isUnconnected())
                        CE = nullptr;
                    CE = inputPin->getNet();
                }
                else if (inputPin->getPinType() == DesignInfo::PinType_SR)
                {
                    if (inputPin->isUnconnected())
                        SR = nullptr;
                    SR = inputPin->getNet();
                }
                else if (inputPin->getPinType() == DesignInfo::PinType_D)
                {
                    // bypass
                }
                else
                {
                    assert(false && "undefined FF input pin type.");
                }
            }
            FFType = curFF->getOriCellType();
        }
 
        inline DesignInfo::DesignNet *getCLK() const
        {
            return CLK;
        }
        inline DesignInfo::DesignNet *getSR() const
        {
            return SR;
        }
        inline DesignInfo::DesignNet *getCE() const
        {
            return CE;
        }
 
        inline DesignInfo::DesignCellType getFFType() const
        {
            return FFType;
        }
        inline const int getId() const
        {
            return id;
        }
 
        inline void addFF(DesignInfo::DesignCell *curFF)
        {
            FFs.push_back(curFF);
        }
 
        inline std::vector<DesignInfo::DesignCell *> &getFFs()
        {
            return FFs;
        }
 
        inline void display()
        {
            if (CLK)
                std::cout << "CLK: " << CLK->getName() << "\n";
            if (SR)
                std::cout << "SR: " << SR->getName() << "\n";
            if (CE)
                std::cout << "CE: " << CE->getName() << "\n";
            std::vector<std::string> DesignCellTypeStr{CELLTYPESTRS};
            std::cout << "CellType: " << DesignCellTypeStr[(int)FFType] << "\n";
        }
 
      private:
        DesignInfo::DesignNet *CLK = nullptr;
        DesignInfo::DesignNet *SR = nullptr;
        DesignInfo::DesignNet *CE = nullptr;
        DesignInfo::DesignCellType FFType;
        std::vector<DesignInfo::DesignCell *> FFs;
        int id = -1;
    };
 
    inline static bool isLUT(DesignCellType cellType)
    {
        return cellType == CellType_LUT6_2 || cellType == CellType_LUT6 || cellType == CellType_LUT5 ||
               cellType == CellType_LUT4 || cellType == CellType_LUT3 || cellType == CellType_LUT2 ||
               cellType == CellType_LUT1;
    }
 
    inline static bool isCarry(DesignCellType cellType)
    {
        return cellType == CellType_CARRY8;
    }
 
    inline static bool isDSP(DesignCellType cellType)
    {
        return cellType == CellType_DSP48E2;
    }
 
    inline static bool isBRAM(DesignCellType cellType)
    {
        return cellType == CellType_RAMB36E2 || cellType == CellType_RAMB18E2 || cellType == CellType_FIFO18E2 ||
               cellType == CellType_FIFO36E2;
    }
 
    inline static bool isMux(DesignCellType cellType)
    {
        return cellType == CellType_MUXF7 || cellType == CellType_MUXF8;
    }
 
    inline static bool isLUTRAM(DesignCellType cellType)
    {
        return (cellType == CellType_RAM32M16 || cellType == CellType_RAM32X1D || cellType == CellType_RAM64X1S ||
                cellType == CellType_RAM64M || cellType == CellType_RAM64X1D || cellType == CellType_RAM32M ||
                cellType == CellType_RAM32X1D || cellType == CellType_RAM32X1S || cellType == CellType_RAM64X1S ||
                cellType == CellType_RAM64M8 || cellType == CellType_RAM256X1D);
    }
 
    inline static bool isFF(DesignCellType cellType)
    {
        return cellType == CellType_FDCE || cellType == CellType_FDPE || cellType == CellType_FDSE ||
               cellType == CellType_LDCE || cellType == CellType_FDRE || cellType == CellType_AND2B1L;
    }
 
    inline static bool isIO(DesignCellType cellType)
    {
        return cellType == CellType_GTHE3_CHANNEL || cellType == CellType_GTHE3_COMMON || cellType == CellType_IOBUF ||
               cellType == CellType_IBUF || cellType == CellType_IBUFDS || cellType == CellType_IOBUFDS ||
               cellType == CellType_IBUFDS_GTE3 || cellType == CellType_IBUF_ANALOG || cellType == CellType_IOBUFE3 ||
 
               cellType == CellType_MMCME3_ADV ||
 
               cellType == CellType_OBUF || cellType == CellType_OBUFT || cellType == CellType_PCIE_3_1 ||
 
               cellType == CellType_BSCANE2 || cellType == CellType_SYSMONE1 || cellType == CellType_RXTX_BITSLICE ||
               cellType == CellType_BITSLICE_CONTROL || cellType == CellType_TX_BITSLICE_TRI ||
               cellType == CellType_OSERDESE3 ||
 
               cellType == CellType_RIU_OR || cellType == CellType_PLLE3_ADV || cellType == CellType_HPIO_VREF ||
               cellType == CellType_OBUFDS_DUAL_BUF;
    }
 
    inline bool isClockBuffer(DesignCellType cellType)
    {
        return cellType == CellType_BUFGCE || cellType == CellType_BUFG_GT || cellType == CellType_BUFG_GT_SYNC ||
               cellType == CellType_BUFGCE_DIV || cellType == CellType_BUFGCTRL;
    }
    inline bool isShifter(DesignCellType cellType)
    {
        return cellType == CellType_SRL16E || cellType == CellType_SRLC32E;
    }
 
    inline bool isLogicRelated(DesignCellType cellType)
    {
        return (isLUT(cellType) || isFF(cellType) || isLUTRAM(cellType) || isBRAM(cellType) || isDSP(cellType) ||
                isShifter(cellType));
    }
 
    // clang-format off
    // clang-format on
    DesignInfo(std::map<std::string, std::string> &JSONCfg, DeviceInfo *deviceInfo);
 
    ~DesignInfo()
    {
        for (auto net : netlist)
            delete net;
        for (auto cell : cells)
            delete cell;
        for (auto CS : controlSets)
            delete CS;
    }
 
    void addPinToNet(DesignPin *curPin);
 
    DesignCellType fromStringToCellType(std::string &cellName, std::string &typeName);
 
    DesignCell *addCell(DesignCell *curCell);
 
    inline void getCLKSRCENetId(DesignInfo::DesignCell *curFF, int &CLKId, int &SRId, int &CEId)
    {
        assert(curFF->isFF());
        CLKId = -1;
        SRId = -1;
        CEId = -1;
        for (auto inputPin : curFF->getInputPins())
        {
            if (inputPin->getPinType() == DesignInfo::PinType_CLK)
            {
                if (!inputPin->isUnconnected())
                    CLKId = inputPin->getNet()->getElementIdInType();
            }
            else if (inputPin->getPinType() == DesignInfo::PinType_E)
            {
                if (!inputPin->isUnconnected())
                    CEId = inputPin->getNet()->getElementIdInType();
            }
            else if (inputPin->getPinType() == DesignInfo::PinType_SR)
            {
                if (!inputPin->isUnconnected())
                    SRId = inputPin->getNet()->getElementIdInType();
            }
            else if (inputPin->getPinType() == DesignInfo::PinType_D)
            {
                // bypass
            }
            else
            {
                assert(false && "undefined FF input pin type.");
            }
        }
    }
 
    inline void getCLKSRCENet(DesignInfo::DesignCell *curFF, DesignNet **CLK, DesignNet **SR, DesignNet **CE)
    {
        assert(curFF->isFF());
        *CLK = nullptr;
        *SR = nullptr;
        *CE = nullptr;
        for (auto inputPin : curFF->getInputPins())
        {
            if (inputPin->getPinType() == DesignInfo::PinType_CLK)
            {
                if (!inputPin->isUnconnected())
                    *CLK = inputPin->getNet();
            }
            else if (inputPin->getPinType() == DesignInfo::PinType_E)
            {
                if (!inputPin->isUnconnected())
                    *CE = inputPin->getNet();
            }
            else if (inputPin->getPinType() == DesignInfo::PinType_SR)
            {
                if (!inputPin->isUnconnected())
                    *SR = inputPin->getNet();
            }
            else if (inputPin->getPinType() == DesignInfo::PinType_D)
            {
                // bypass
            }
            else
            {
                assert(false && "undefined FF input pin type.");
            }
        }
    }
 
    void loadClocks(std::string clockFileName);
 
    void updateFFControlSets();
 
    void enhanceFFControlSetNets();
 
    inline std::vector<ControlSetInfo *> &getControlSets()
    {
        return controlSets;
    }
 
    inline int getFFControlSetId(DesignCell *curFF)
    {
        assert(curFF->isFF());
        assert(FFId2ControlSetId[curFF->getCellId()] >= 0);
        return FFId2ControlSetId[curFF->getCellId()];
    }
 
    void loadUserDefinedClusterNets();
 
    inline int getNumCells()
    {
        return cells.size();
    };
    inline int getNumNets()
    {
        return netlist.size();
    };
 
    inline std::vector<DesignCell *> &getCells()
    {
        return cells;
    };
    inline std::vector<DesignNet *> &getNets()
    {
        return netlist;
    };
    inline std::vector<DesignPin *> &getPins()
    {
        return pins;
    };
 
    void resetNetEnhanceRatio()
    {
        for (auto net : netlist)
            net->resetEnhanceRatio();
    }
 
    void printStat(bool verbose = false);
 
    inline DesignCell *getCell(std::string &tmpName)
    {
        if (name2Cell.find(tmpName) == name2Cell.end())
        {
            std::cout << "cannot find cell:" << tmpName << "\n";
            return nullptr;
        }
        return name2Cell[tmpName];
    }
 
    inline DesignNet *getNet(std::string &tmpName)
    {
        if (name2Net.find(tmpName) == name2Net.end())
        {
            std::cout << "cannot find net:" << tmpName << "\n";
            return nullptr;
        }
        return name2Net[tmpName];
    }
 
    inline std::vector<std::vector<DesignCell *>> &getPredefinedClusters()
    {
        return predefinedClusters;
    }
 
    inline std::map<DesignCellType, std::vector<DesignCell *>> &getType2Cells()
    {
        return type2Cells;
    }
 
    void resetLUTFFDeterminedOccupation()
    {
        LUTFFDeterminedOccupation.clear();
        LUTFFDeterminedOccupation.resize(cells.size(), -1);
    }
 
    inline int getDeterminedOccupation(int cellId)
    {
        return LUTFFDeterminedOccupation[cellId];
    }
 
    inline void setDeterminedOccupation(int cellId, int occupation)
    {
        LUTFFDeterminedOccupation[cellId] = occupation;
    }
 
    inline bool isDesignClock(DesignNet *tmpNet)
    {
        return clockSet.find(tmpNet) != clockSet.end();
    }
 
    inline std::vector<DesignNet *> &getClocksInDesign()
    {
        return clocks;
    }
 
    inline std::set<DesignCell *> &getCellsUnderClock(DesignNet *clock)
    {
        assert(clock2Cells.find(clock) != clock2Cells.end());
        return clock2Cells[clock];
    }
 
  private:
    std::vector<DesignNet *> netlist;
    std::vector<DesignCell *> cells;
    std::vector<DesignPin *> pins;
    std::map<std::string, DesignNet *> name2Net;
    std::map<std::string, int> aliasNet2AliasNetId;
    std::map<std::string, DesignCell *> name2Cell;
 
    std::vector<std::vector<DesignCell *>> predefinedClusters;
    std::map<DesignCellType, std::vector<DesignCell *>> type2Cells;
 
    std::set<std::pair<DesignPin *, DesignPin *>> connectedPinsWithSmallNet;
 
    std::vector<int> LUTFFDeterminedOccupation;
 
    std::map<std::tuple<int, int, int, int>, int> CLKSRCEFFType2ControlSetInfoId;
 
    std::vector<int> FFId2ControlSetId;
 
    std::vector<ControlSetInfo *> controlSets;
    std::vector<DesignNet *> clocks;
    std::set<DesignNet *> clockSet;
 
    std::map<DesignNet *, std::set<DesignCell *>> clock2Cells;
 
    std::map<std::string, std::string> &JSONCfg;
    std::string designArchievedTextFileName;
};
 
std::ostream &operator<<(std::ostream &os, DesignInfo::DesignCell *cell);
std::ostream &operator<<(std::ostream &os, DesignInfo::DesignPin *pin);
#endif