AMF-Placer
2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
|
Go to the documentation of this file.
25 #ifndef _PlacementTimingInfo
26 #define _PlacementTimingInfo
37 #include <semaphore.h>
84 for (
auto edge :
edges)
86 for (
auto node :
nodes)
240 return a->getSink()->getBackwardLevel() < b->getSink()->getBackwardLevel();
261 return a->getSource()->getForwardLevel() < b->getSource()->getForwardLevel();
534 nodes.push_back(timingNode);
560 auto newEdge =
new TimingEdge(
nodes[idA],
nodes[idB], srcPin, sinkPin, net,
edges.size());
561 newEdge->setDelay(
delay);
562 edges.push_back(newEdge);
564 nodes[idB]->addInEdge(newEdge);
565 nodes[idA]->addOutEdge(newEdge);
578 if (level > 0 && curNode == startNode)
580 for (
auto nodeId : nodeInPath)
582 std::cout <<
nodes[nodeId]->getDesignNode()->getName() <<
" =>" <<
nodes[nodeId]->checkIsRegister()
584 std::cout <<
nodes[nodeId]->getDesignNode() <<
"\n";
588 for (
auto outEdge :
nodes[curNode]->getOutEdges())
590 int nextId = outEdge->getSink()->getId();
592 if (!
nodes[nextId]->checkIsRegister())
595 nodeInPath.push_back(nextId);
597 nodeInPath.pop_back();
632 for (
unsigned int i = 0;
i <
getNodes().size();
i++)
670 for (
auto tmpNode :
nodes)
672 tmpNode->calcLongestPath();
673 tmpNode->getDesignNode()->setTimingLength(tmpNode->getLongestPathLength());
678 return (a->getLongestPathLength() == b->getLongestPathLength())
679 ? (a->getForwardLevel() < b->getForwardLevel())
680 : (a->getLongestPathLength() > b->getLongestPathLength());
689 if (
nodes[
id]->getInEdges().size() == 0)
694 [](TimingNode *a, TimingNode *b) ->
bool {
695 return (a->getLatestInputArrival() > b->getLatestInputArrival());
727 std::vector<int>
BFSFromNode(
int startNodeId,
int pathLenThr,
unsigned sizeThr, std::set<int> &exceptionCells);
737 std::vector<int>
DFSFromNode(
int startNodeId,
int pathLenThr,
unsigned sizeThr, std::set<int> &exceptionCells,
738 int fanoutThr = 10000000);
void setForwardLevel(int _forwardLevel)
Set the data path forward level of the node for later propagation.
float getLatestInputArrival()
Get the latest arrival time to the output of this timing node.
DesignInfo::DesignPin * getSourcePin()
std::vector< TimingEdge * > & getInEdges()
Get the inward edges to this TimingNode.
TimingNode(nodeType *designNode, int id)
Construct a new Timing Node object.
std::vector< int > traceBackFromNode(int targetId)
find the longest path from a register to the target node (id)
int forwardLevel
the distance toward the farthest predecessor register based on the path length (instead of delay)
std::vector< TimingGraph< DesignInfo::DesignCell >::TimingNode * > & getSimplePlacementTimingInfo_PathLenSorted()
void updateCriticalPath()
std::vector< TimingNode * > & getNodes()
void setSlowestPredecessorId(int _slowestPredecessorId)
Set the slowest predecessor node Id.
void setClockPeriod(float _clockPeriod)
Set the clock period.
std::map< DesignInfo::DesignNet *, float > clockNet2Period
PlacementTimingInfo is the container which record the timing information related to placement.
void setLongestPathLength()
Set the Longest Path Length for each TimingNode in the TimingGraph and get a sorted vector of TimingN...
std::vector< TimingEdge * > inEdges
a design net (hyperedge) defined in the design, connecting to pins of cells
float latestOutputArrival
void setRequiredArrivalTime(float _requiredArrival)
Set the required arrival time.
void setIsRegister()
indicate that this node is a register node
int mediumPathThresholdLevel
std::vector< int > DFSFromNode(int startNodeId, int pathLenThr, unsigned sizeThr, std::set< int > &exceptionCells, int fanoutThr=10000000)
DFS the sucessors(predecessors) of a node in the long paths.
TimingGraph(PlacementTimingInfo *timingInfo)
Construct a new empty Timing Graph object.
float getClockPeriod()
Get the clock period.
A design pin on a design cell connected to a net.
int longestPathLength
the length of the longest path containing this TimingNode
DesignInfo::DesignPin * getSinkPin()
void setInitialRequiredArrivalTime(float _requiredArrival)
Set the required arrival time.
void setDestLevel(int _destLevel)
void backwardLevelization()
propogate the backward level of each TimingNode backward level of a TimingNode is the distance toward...
TimingEdge(TimingNode *srcNode, TimingNode *sinkNode, DesignInfo::DesignPin *srcPin, DesignInfo::DesignPin *sinkPin, DesignInfo::DesignNet *net=nullptr, int id=-1)
Construct a new Timing Edge object.
std::vector< std::vector< int > > backwardlevel2NodeIds
levelized nodes in difference backward level
void setInnerDelay(float _innerDelay)
Set the inner delay.
void calcLongestPath()
calculate the length of the longest path containing this TimingNode
This header file contains the classes of data for a standalone design netlist.
std::vector< TimingEdge * > outEdges
void setBackwardLevel(int _backwardLevel)
std::vector< TimingEdge * > & getOutEdges()
Get the outward edges from this TimingNode.
std::vector< TimingEdge * > & getEdges()
int longPathThresholdLevel
float getCriticalPathDelay()
TimingNode is the node in TimingGraph, which could be pin or cell in the design netlist.
This header file contains the classes of data for a standalone device.
void setLongPathThrRatio(float _r)
void setLatestInputArrival(float _latestInputArrival)
Set the latest arrival time to the output of this timing node.
PlacementTimingInfo * timingInfo
float getRequiredArrivalTime()
Get the required arrival time.
std::vector< TimingNode * > & getSortedTimingEndpoints()
std::vector< std::vector< int > > forwardlevel2NodeIds
levelized nodes in difference forward level
DesignInfo::DesignPin * srcPin
std::vector< int > backTraceDelayLongestPathFromNode(int curNodeId)
backtrace the longest delay path from the node
void findALoopFromNode(std::vector< int > &nodeInPath, int startNode, int curNode, int level)
find loop from a node in timing graph (for debug)
int getSlowestPredecessorId()
Get the slowest predecessor node Id.
void sortInEdgesByForwardLevel()
sort the inward edges by their source node forward level
nodeType * designNode
the pointer linked to the design element (pin or cell)
DesignInfo::DesignNet * net
void forwardLevelization()
propogate the forward level of each TimingNode forward level of a TimingNode is the distance toward t...
void propogateArrivalTime()
propogate the timing delay along the TimingEdge
void setEarlestSuccessorId(int _earliestSuccessorId)
Set the earliest successor node Id.
std::vector< TimingNode * > delaySortedTimingEndpointNodes
int getForwardLevel()
Get the distance toward the farthest predecessor register based on the path length (instead of delay)
int getMediumPathThresholdLevel()
void addEdgeBetween(int idA, int idB, DesignInfo::DesignPin *srcPin, DesignInfo::DesignPin *sinkPin, DesignInfo::DesignNet *net=nullptr, float delay=0.0)
add a TimingEdge into TimingGraph based on some related information
DeviceInfo * getDeviceInfo()
int backwardLevel
the distance toward the farthest successor register based on the path length (instead of delay)
int getMediumPathThresholdLevel()
Get the medium path threshold level.
std::map< int, float > cellId2Period
a directed graph for timing analysis
void setClockPeriod(float _clockPeriod)
float getInnerDelay()
Get the inner delay.
std::vector< TimingNode * > nodes
float getLatestOutputArrival()
void sortOutEdgesByBackwardLevel()
sort the outward edges by their sink node backward level
std::vector< TimingNode * > & getPathLenSortedNodes()
std::vector< TimingGraph< DesignInfo::DesignCell >::TimingNode * > & getSimplePlacementTimingInfo()
Get the Simple Timing Info object which regard design cells as timing nodes.
int getCriticalEndPoint()
Information class related to FPGA device, including the details of BEL/Site/Tile/ClockRegion.
int getLongPathThresholdLevel()
Get the long path threshold level.
std::vector< TimingNode * > pathLenSortedNodes
float innerDelay
the node can have internal delay (e.g., cell delay)
int getLongestPathLength()
Get the length of the longest path containing this TimingNode.
std::vector< TimingEdge * > edges
PlacementTimingInfo(DesignInfo *designInfo, DeviceInfo *deviceInfo, std::map< std::string, std::string > &JSONCfg)
Construct a new Placement Timing Info object based on the information of design and device.
std::vector< int > traceForwardFromNode(int targetId)
find the longest path from the target node (id) to a register
void insertTimingNode(TimingNode *timingNode)
insert a TimingNode into this TimingGraph
int getEarlestSuccessorId()
Get the earliest successor node Id.
std::map< std::string, std::string > & JSONCfg
DesignInfo::DesignPin * sinkPin
void addOutEdge(TimingEdge *tmpEdge)
void setClusterId(int _clusterId)
bool checkIsRegister()
check if the node is a register node
Information related to FPGA designs, including design cells and their interconnections.
void setDelay(float _delay)
void buildSimpleTimingGraph()
build a simple timing graph, where the inner delay between pin paris for an element will be identical
void backPropogateRequiredArrivalTime()
back propogate the required arrival time
TimingEdge records a directed interconnection relationship between two TimingNode....
int getLongPathThresholdLevel()
void sortedEndpointByDelay()
int getBackwardLevel()
Get the distance toward the farthest successor register based on the path length (instead of delay)
void setLatestOutputArrival(float _latestOutputArrival)
nodeType * getDesignNode()
TimingGraph< DesignInfo::DesignCell > * getSimplePlacementTimingGraph()
Get the Simple Placement Timing Graph object.
void addInEdge(TimingEdge *tmpEdge)
TimingGraph< DesignInfo::DesignCell > * simpleTimingGraph
std::vector< int > BFSFromNode(int startNodeId, int pathLenThr, unsigned sizeThr, std::set< int > &exceptionCells)
BFS the sucessors(predecessors) of a node in the long paths.