This inheritance list is sorted roughly, but not completely, alphabetically:

[detail level 12]

CWirelengthOptimizer::_CellWithScore
CIncrementalBELPacker::_CellWithScore
CPlacementInfo::_ClockNetCoverage	Retangular clock region coverage of a clock net
CPlacementInfo::PlacementMacro::_fixedPlacementInfo_inMacro	Some constaints of elements' relative locations are defined by the design. We need to record this
CPlacementInfo::PlacementNet::_pinOffset
CWirelengthOptimizer::_PUWithScore
CIncrementalBELPacker::_PUWithScore
CParallelCLBPacker::_PUWithScore	Helper struct for candidate site sorting
CParallelCLBPacker::_siteWithScore	Helper struct for candidate site sorting
CWirelengthOptimizer::_slackEnhanceTuple
CAMFPlacer	AMFPlacer is an analytical mixed-size FPGA placer
▼Carray
CIncrementalBELPacker::FFLocation	FFLocation records the FF cell pointer and the location of the FF cell for kdt::KDTree construction which can help to find neighbors for cells
CParallelCLBPacker::PULocation	PULocation is a helper class to find the neighbor PlacementUnits with KD-Tree
CPlacementInfo::CellBinInfo	Record the bin information for a cell (BELtype, column/row, resource demand)
CCLBLegalizer	CLBLegalizer maps CLBs (each of which consists of one site) to legal location. e.g. LUTRAM, except those CLBs in CARRY8_Chain
CDeviceInfo::ClockColumn	Column of site in clock region
CDeviceInfo::ClockRegion	Class for clock regions on FPGA
CPlacementInfo::ClusterNet	The net between the objects of ClusterUnit class
CClusterPlacer	ClusterPlacer will cluster nodes in the given netlist and place the clusters on the device based on simulated-annealing as initial placement
CPlacementInfo::ClusterUnit	Group of PlacementUnits
CPlacementInfo::CompatiblePlacementTable	Describes the type mapping from design to device, where a cell can be placed (which BEL in which site)
CDesignInfo::ControlSetInfo	A control set is a combination of CLK, CE and SR signal. It could be nullptr (not related to control set)
▼CDesignInfo::DesignElement	Basic class of element in a design
CDesignInfo::DesignCell	DesignCell in design netlist, DesignPin objects of which might connect to DesignNet objects
CDesignInfo::DesignNet	Design net (hyperedge) defined in the design, connecting to pins of cells
CDesignInfo::DesignPin	A design pin on a design cell connected to a net
CDesignInfo	Information related to FPGA designs, including design cells and their interconnections
▼CDeviceInfo::DeviceElement	Basic class of device element
CDeviceInfo::DeviceBEL	BEL(Basic Element of Logic), the smallest undividable element
CDeviceInfo::DeviceSite	Site class for site on device
CDeviceInfo::DeviceTile	A tile is a combination of sites
CDeviceInfo	Information class related to FPGA device, including the details of BEL/Site/Tile/ClockRegion
CDeviceInfo::DeviceSite::DeviceSitePinInfos	Class record the pin on the site boundary
CGeneralSpreader::SpreadRegion::expandOp	Struct to describe the expanding operation for the SpreadRegion
CExternalProcessFunc	ExternalProcessFunc is a wrapper of an external exectable for multi-process scenario with shared memory
CGeneralSpreader	GeneralSpreader accounts for the cell spreading, which controls the cell density of specific resource type, under the device constraints for specific regions
CGlobalPlacer	GlobalPlacer accounts for the general iterations in global placement
CGraphPartitioner< NodeList, NetList >	GraphPartitioner will recursively bi-partition the netlist (which could be netlist of clusters) based on connectivitity and the net weights
CGraphPartitioner< std::vector< PlacementInfo::ClusterUnit * >, std::vector< PlacementInfo::ClusterNet * > >
CGraphPartitioner< std::vector< PlacementInfo::PlacementUnit * >, std::vector< PlacementInfo::PlacementNet * > >
CIncrementalBELPacker	IncrementalBELPacker incrementally packs some LUTs/FFs during global placement based on their distance, interconnection density and compatibility
CInitialPacker	InitialPacker will identify macros from the design netlist based on pattern matching
CPlacementInfo::Location
CPlacementInfo::PlacementSiteTypeInfo::location
CMacroLegalizer	MacroLegalizer maps DSP/BRAM/CARRY macros to legal location
CMinCostBipartiteMatcher
▼Cobject
CexportDeviceLocation.siteInfo
CVivadoGraphUtil.VivadoCell
CVivadoGraphUtil.VivadoCoreCluster
CVivadoGraphUtil.VivadoNet
CVivadoGraphUtil.VivadoPatternCluster
CVivadoGraphUtil.VivadoPatternClusterSeq
CVivadoGraphUtil.VivadoPin
CInitialPacker::PackedControlSet	Control set information container used during initial packing
CParallelCLBPacker::PackedControlSet	PackedControlSet stores the data of a combination of FFs within one control set (clock enable/preset-reset/clock) that can be packed in a site
CPacking_Netcompare
CPacking_PUcompare	Utility struct for the comparison between PlacementInfo::PlacementUnit according to PU ID
CParallelCLBPacker::PackingCLBSite::PackingCLBCluster	PackingCLBCluster is a container of cells/PlacementUnits which can be packed in the corresponding CLB site
CParallelCLBPacker::PackingCLBSite	PackingCLBSite is a container for the packing information (parameters, candidates and packing status) of a specific DeviceInfo::DeviceSite
CParallelCLBPacker	ParallelCLBPacker will finally pack LUT/FF/MUX/CARRY elements into legal CLB sites in a parallel approach
CPlacementInfo::PlacementBinInfo	BEL bin for global placement for a specific shared BEL type
CPlacementInfo::PlacementHybridBinInfo	BEL bin for global placement for multiple specific shared BEL types
CPlacementInfo	Information related to FPGA placement (wirelength optimization, cell spreading, legalization, packing)
CPlacementInfo::PlacementNet	Placement net, compared to design net, includes information related to placement
CPlacementInfo::PlacementSiteBinInfo	Site bin for global placement for some specific Site types
CPlacementInfo::PlacementSiteTypeInfo	Information for a site, e.g. what BEL in site and where are these kind of sites
CPlacementTimingInfo	PlacementTimingInfo is the container which record the timing information related to placement
CPlacementTimingOptimizer
▼CPlacementInfo::PlacementUnit	Movement unit in placement with information of location and resource demand
CPlacementInfo::PlacementMacro	Fixed group of multiple standard cells with constraints of their relative locations
CPlacementInfo::PlacementUnpackedCell	Smallest, indivisible, representable component. It will include only one standard cell
CProcessFuncInterface
CQPSolverWrapper
CSAPlacer
CParallelCLBPacker::PackingCLBSite::SiteBELMapping	SiteBELMapping is a contain recording the mapping between cells and BELs
CInitialPacker::SiteBELMapping	SiteBELMapping is a contain recording the mapping between cells and BELs
CQPSolverWrapper::solverDataType
CQPSolverWrapper::solverSettingsType
CGeneralSpreader::SpreadRegion	SpreadRegion is an object that record cell spreading region information, including boundaries, cells, bins, and spreading boxes
▼Cstreambuf
CFILEbuf
CGeneralSpreader::SpreadRegion::SubBox	SubBox is the exact container which is the object for bi-partitioning-based cell spreading
CPlacementTimingInfo::TimingGraph< nodeType >::TimingEdge	TimingEdge records a directed interconnection relationship between two TimingNode. It is a point-to-point information instead of HyperEdge
CPlacementTimingInfo::TimingGraph< nodeType >	Directed graph for timing analysis
CPlacementTimingInfo::TimingGraph< DesignInfo::DesignCell >
CPlacementTimingInfo::TimingGraph< nodeType >::TimingNode	TimingNode is the node in TimingGraph, which could be pin or cell in the design netlist
CWirelengthOptimizer	WirelengthOptimizer builds numerical models based on the element locations and calls solvers to find an optimal solution of the placement