- Generated by
1.8.18
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AMF-Placer
2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
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| ▼NexportDeviceLocation | |
| CsiteInfo | |
| ▼NVivadoGraphUtil | |
| CVivadoCell | |
| CVivadoCoreCluster | |
| CVivadoNet | |
| CVivadoPatternCluster | |
| CVivadoPatternClusterSeq | |
| CVivadoPin | |
| CAMFPlacer | AMFPlacer is an analytical mixed-size FPGA placer |
| CCLBLegalizer | CLBLegalizer maps CLBs (each of which consists of one site) to legal location. e.g. LUTRAM, except those CLBs in CARRY8_Chain |
| CClusterPlacer | ClusterPlacer will cluster nodes in the given netlist and place the clusters on the device based on simulated-annealing as initial placement |
| ▼CDesignInfo | Information related to FPGA designs, including design cells and their interconnections |
| CControlSetInfo | A control set is a combination of CLK, CE and SR signal. It could be nullptr (not related to control set) |
| CDesignCell | DesignCell in design netlist, DesignPin objects of which might connect to DesignNet objects |
| CDesignElement | Basic class of element in a design |
| CDesignNet | Design net (hyperedge) defined in the design, connecting to pins of cells |
| CDesignPin | A design pin on a design cell connected to a net |
| ▼CDeviceInfo | Information class related to FPGA device, including the details of BEL/Site/Tile/ClockRegion |
| CClockColumn | Column of site in clock region |
| CClockRegion | Class for clock regions on FPGA |
| CDeviceBEL | BEL(Basic Element of Logic), the smallest undividable element |
| CDeviceElement | Basic class of device element |
| ▼CDeviceSite | Site class for site on device |
| CDeviceSitePinInfos | Class record the pin on the site boundary |
| CDeviceTile | A tile is a combination of sites |
| CExternalProcessFunc | ExternalProcessFunc is a wrapper of an external exectable for multi-process scenario with shared memory |
| CFILEbuf | |
| ▼CGeneralSpreader | GeneralSpreader accounts for the cell spreading, which controls the cell density of specific resource type, under the device constraints for specific regions |
| ▼CSpreadRegion | SpreadRegion is an object that record cell spreading region information, including boundaries, cells, bins, and spreading boxes |
| CexpandOp | Struct to describe the expanding operation for the SpreadRegion |
| CSubBox | SubBox is the exact container which is the object for bi-partitioning-based cell spreading |
| CGlobalPlacer | GlobalPlacer accounts for the general iterations in global placement |
| CGraphPartitioner | GraphPartitioner will recursively bi-partition the netlist (which could be netlist of clusters) based on connectivitity and the net weights |
| ▼CIncrementalBELPacker | IncrementalBELPacker incrementally packs some LUTs/FFs during global placement based on their distance, interconnection density and compatibility |
| C_CellWithScore | |
| C_PUWithScore | |
| CFFLocation | FFLocation records the FF cell pointer and the location of the FF cell for kdt::KDTree construction which can help to find neighbors for cells |
| ▼CInitialPacker | InitialPacker will identify macros from the design netlist based on pattern matching |
| CPackedControlSet | Control set information container used during initial packing |
| CSiteBELMapping | SiteBELMapping is a contain recording the mapping between cells and BELs |
| CMacroLegalizer | MacroLegalizer maps DSP/BRAM/CARRY macros to legal location |
| CMinCostBipartiteMatcher | |
| CPacking_Netcompare | |
| CPacking_PUcompare | Utility struct for the comparison between PlacementInfo::PlacementUnit according to PU ID |
| ▼CParallelCLBPacker | ParallelCLBPacker will finally pack LUT/FF/MUX/CARRY elements into legal CLB sites in a parallel approach |
| C_PUWithScore | Helper struct for candidate site sorting |
| C_siteWithScore | Helper struct for candidate site sorting |
| CPackedControlSet | PackedControlSet stores the data of a combination of FFs within one control set (clock enable/preset-reset/clock) that can be packed in a site |
| ▼CPackingCLBSite | PackingCLBSite is a container for the packing information (parameters, candidates and packing status) of a specific DeviceInfo::DeviceSite |
| CPackingCLBCluster | PackingCLBCluster is a container of cells/PlacementUnits which can be packed in the corresponding CLB site |
| CSiteBELMapping | SiteBELMapping is a contain recording the mapping between cells and BELs |
| CPULocation | PULocation is a helper class to find the neighbor PlacementUnits with KD-Tree |
| ▼CPlacementInfo | Information related to FPGA placement (wirelength optimization, cell spreading, legalization, packing) |
| C_ClockNetCoverage | Retangular clock region coverage of a clock net |
| CCellBinInfo | Record the bin information for a cell (BELtype, column/row, resource demand) |
| CClusterNet | The net between the objects of ClusterUnit class |
| CClusterUnit | Group of PlacementUnits |
| CCompatiblePlacementTable | Describes the type mapping from design to device, where a cell can be placed (which BEL in which site) |
| CLocation | |
| CPlacementBinInfo | BEL bin for global placement for a specific shared BEL type |
| CPlacementHybridBinInfo | BEL bin for global placement for multiple specific shared BEL types |
| ▼CPlacementMacro | Fixed group of multiple standard cells with constraints of their relative locations |
| C_fixedPlacementInfo_inMacro | Some constaints of elements' relative locations are defined by the design. We need to record this |
| ▼CPlacementNet | Placement net, compared to design net, includes information related to placement |
| C_pinOffset | |
| CPlacementSiteBinInfo | Site bin for global placement for some specific Site types |
| ▼CPlacementSiteTypeInfo | Information for a site, e.g. what BEL in site and where are these kind of sites |
| Clocation | |
| CPlacementUnit | Movement unit in placement with information of location and resource demand |
| CPlacementUnpackedCell | Smallest, indivisible, representable component. It will include only one standard cell |
| ▼CPlacementTimingInfo | PlacementTimingInfo is the container which record the timing information related to placement |
| ▼CTimingGraph | Directed graph for timing analysis |
| CTimingEdge | TimingEdge records a directed interconnection relationship between two TimingNode. It is a point-to-point information instead of HyperEdge |
| CTimingNode | TimingNode is the node in TimingGraph, which could be pin or cell in the design netlist |
| CPlacementTimingOptimizer | |
| CProcessFuncInterface | |
| ▼CQPSolverWrapper | |
| CsolverDataType | |
| CsolverSettingsType | |
| CSAPlacer | |
| ▼CWirelengthOptimizer | WirelengthOptimizer builds numerical models based on the element locations and calls solvers to find an optimal solution of the placement |
| C_CellWithScore | |
| C_PUWithScore | |
| C_slackEnhanceTuple |
1.8.18