DesignInfo::DesignCell Member List

This is the complete list of members for DesignInfo::DesignCell, including all inherited members.

addClockNet(DesignNet *aClockNet)	DesignInfo::DesignCell	inline
addNetForPin(DesignPin *_pinPtr, DesignNet *_netPtr)	DesignInfo::DesignCell
addPin(DesignPin *_pinPtr)	DesignInfo::DesignCell
cellType	DesignInfo::DesignCell	private
checkHasDSPReg()	DesignInfo::DesignCell	inline
clockNetPtrs	DesignInfo::DesignCell	private
controlSetInfo	DesignInfo::DesignCell	private
DesignCell(const std::string &name, DesignElement *parentPtr, DesignCellType cellType, int id)	DesignInfo::DesignCell	inline
DesignCell(const std::string &name, DesignCellType cellType, int id)	DesignInfo::DesignCell	inline
DesignCell(bool isVirtual, DesignCellType cellType, int id)	DesignInfo::DesignCell	inline
DesignCell(bool isVirtual, const std::string &name, DesignCellType cellType, int id)	DesignInfo::DesignCell	inline
DesignElement(const std::string &name, DesignElement *parentPtr, DesignElementType type, int id)	DesignInfo::DesignElement	inline
DesignElement(const std::string &name, DesignElementType type, int id)	DesignInfo::DesignElement	inline
DesignElement(bool isVirtual, DesignElementType type, int id)	DesignInfo::DesignElement	inline
DesignElement(bool isVirtual, const std::string &_name, DesignElementType type, int id)	DesignInfo::DesignElement	inline
getCellId()	DesignInfo::DesignCell	inline
getCellType()	DesignInfo::DesignCell	inline
getClockNets()	DesignInfo::DesignCell	inline
getControlSetInfo()	DesignInfo::DesignCell	inline
getElementIdInType()	DesignInfo::DesignElement	inline
getElementType()	DesignInfo::DesignElement	inline
getInputNets()	DesignInfo::DesignCell	inline
getInputPins()	DesignInfo::DesignCell	inline
getName() const	DesignInfo::DesignElement	inline
getOriCellType()	DesignInfo::DesignCell	inline
getOutputNets()	DesignInfo::DesignCell	inline
getOutputPins()	DesignInfo::DesignCell	inline
getParentPtr()	DesignInfo::DesignElement	inline
getPins()	DesignInfo::DesignCell	inline
getTimingLength()	DesignInfo::DesignCell	inline
hasDSPReg	DesignInfo::DesignCell	private
id	DesignInfo::DesignElement	private
inputNetPtrs	DesignInfo::DesignCell	private
inputPinPtrs	DesignInfo::DesignCell	private
isBRAM()	DesignInfo::DesignCell	inline
isCarry()	DesignInfo::DesignCell	inline
isClockBuffer()	DesignInfo::DesignCell	inline
isDSP()	DesignInfo::DesignCell	inline
isFF()	DesignInfo::DesignCell	inline
isIO()	DesignInfo::DesignCell	inline
isLogicRelated()	DesignInfo::DesignCell	inline
isLUT()	DesignInfo::DesignCell	inline
isLUT6()	DesignInfo::DesignCell	inline
isLUTRAM()	DesignInfo::DesignCell	inline
isMux()	DesignInfo::DesignCell	inline
isShift()	DesignInfo::DesignCell	inline
isShifter()	DesignInfo::DesignCell	inline
isTimingEndPoint()	DesignInfo::DesignCell	inline
isVirtual	DesignInfo::DesignCell	private
isVirtualCell()	DesignInfo::DesignCell	inline
name	DesignInfo::DesignElement	private
netNames	DesignInfo::DesignCell	private
netPtrs	DesignInfo::DesignCell	private
oriCellType	DesignInfo::DesignCell	private
originallyIsLUTRAM()	DesignInfo::DesignCell	inline
outputNetPtrs	DesignInfo::DesignCell	private
outputPinPtrs	DesignInfo::DesignCell	private
parentPtr	DesignInfo::DesignElement	private
pinNames	DesignInfo::DesignCell	private
pinPtrs	DesignInfo::DesignCell	private
setControlSetInfo(ControlSetInfo *_controlSetInfo)	DesignInfo::DesignCell	inline
setHasDSPReg(bool _hasDSPReg)	DesignInfo::DesignCell	inline
setTimingLength(int _timingLength)	DesignInfo::DesignCell	inline
setVirtualType(DesignCellType NewCellType)	DesignInfo::DesignCell	inline
timingLength	DesignInfo::DesignCell	private
type	DesignInfo::DesignElement	private
~DesignCell()	DesignInfo::DesignCell	inline
~DesignElement()	DesignInfo::DesignElement	inlinevirtual