AMF-Placer  2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
DesignInfo Member List

This is the complete list of members for DesignInfo, including all inherited members.

addCell(DesignCell *curCell)DesignInfo
addPinToNet(DesignPin *curPin)DesignInfo
aliasNet2AliasNetIdDesignInfoprivate
cellsDesignInfoprivate
CellType_AND2B1L enum valueDesignInfo
CellType_BITSLICE_CONTROL enum valueDesignInfo
CellType_BSCANE2 enum valueDesignInfo
CellType_BUFG_GT enum valueDesignInfo
CellType_BUFG_GT_SYNC enum valueDesignInfo
CellType_BUFGCE enum valueDesignInfo
CellType_BUFGCE_DIV enum valueDesignInfo
CellType_BUFGCTRL enum valueDesignInfo
CellType_CARRY8 enum valueDesignInfo
CellType_DSP48E2 enum valueDesignInfo
CellType_FDCE enum valueDesignInfo
CellType_FDPE enum valueDesignInfo
CellType_FDRE enum valueDesignInfo
CellType_FDSE enum valueDesignInfo
CellType_FIFO18E2 enum valueDesignInfo
CellType_FIFO36E2 enum valueDesignInfo
CellType_GTHE3_CHANNEL enum valueDesignInfo
CellType_GTHE3_COMMON enum valueDesignInfo
CellType_HPIO_VREF enum valueDesignInfo
CellType_IBUF enum valueDesignInfo
CellType_IBUF_ANALOG enum valueDesignInfo
CellType_IBUFDS enum valueDesignInfo
CellType_IBUFDS_GTE3 enum valueDesignInfo
CellType_IOBUF enum valueDesignInfo
CellType_IOBUFDS enum valueDesignInfo
CellType_IOBUFE3 enum valueDesignInfo
CellType_LDCE enum valueDesignInfo
CellType_LUT1 enum valueDesignInfo
CellType_LUT2 enum valueDesignInfo
CellType_LUT3 enum valueDesignInfo
CellType_LUT4 enum valueDesignInfo
CellType_LUT5 enum valueDesignInfo
CellType_LUT6 enum valueDesignInfo
CellType_LUT6_2 enum valueDesignInfo
CellType_MMCME3_ADV enum valueDesignInfo
CellType_MUXF7 enum valueDesignInfo
CellType_MUXF8 enum valueDesignInfo
CellType_OBUF enum valueDesignInfo
CellType_OBUFDS_DUAL_BUF enum valueDesignInfo
CellType_OBUFT enum valueDesignInfo
CellType_OSERDESE3 enum valueDesignInfo
CellType_PCIE_3_1 enum valueDesignInfo
CellType_PLLE3_ADV enum valueDesignInfo
CellType_RAM256X1D enum valueDesignInfo
CellType_RAM32M enum valueDesignInfo
CellType_RAM32M16 enum valueDesignInfo
CellType_RAM32X1D enum valueDesignInfo
CellType_RAM32X1S enum valueDesignInfo
CellType_RAM64M enum valueDesignInfo
CellType_RAM64M8 enum valueDesignInfo
CellType_RAM64X1D enum valueDesignInfo
CellType_RAM64X1S enum valueDesignInfo
CellType_RAMB18E2 enum valueDesignInfo
CellType_RAMB36E2 enum valueDesignInfo
CellType_RIU_OR enum valueDesignInfo
CellType_RXTX_BITSLICE enum valueDesignInfo
CellType_SRL16E enum valueDesignInfo
CellType_SRLC32E enum valueDesignInfo
CellType_SYSMONE1 enum valueDesignInfo
CellType_TX_BITSLICE_TRI enum valueDesignInfo
CLKSRCEFFType2ControlSetInfoIdDesignInfoprivate
clock2CellsDesignInfoprivate
clocksDesignInfoprivate
clockSetDesignInfoprivate
connectedPinsWithSmallNetDesignInfoprivate
controlSetsDesignInfoprivate
designArchievedTextFileNameDesignInfoprivate
DesignCellType enum nameDesignInfo
DesignCellTypeStrDesignInfo
DesignElementType enum nameDesignInfo
DesignInfo(std::map< std::string, std::string > &JSONCfg, DeviceInfo *deviceInfo)DesignInfo
DesignPinType enum nameDesignInfo
ElementType_cell enum valueDesignInfo
ElementType_graph enum valueDesignInfo
ElementType_net enum valueDesignInfo
ElementType_pin enum valueDesignInfo
enhanceFFControlSetNets()DesignInfo
FFId2ControlSetIdDesignInfoprivate
FFSRCompatible(DesignCellType typeA, DesignCellType typeB)DesignInfoinlinestatic
fromStringToCellType(std::string &cellName, std::string &typeName)DesignInfo
getCell(std::string &tmpName)DesignInfoinline
getCells()DesignInfoinline
getCellsUnderClock(DesignNet *clock)DesignInfoinline
getCLKSRCENet(DesignInfo::DesignCell *curFF, DesignNet **CLK, DesignNet **SR, DesignNet **CE)DesignInfoinline
getCLKSRCENetId(DesignInfo::DesignCell *curFF, int &CLKId, int &SRId, int &CEId)DesignInfoinline
getClocksInDesign()DesignInfoinline
getControlSets()DesignInfoinline
getDeterminedOccupation(int cellId)DesignInfoinline
getFFControlSetId(DesignCell *curFF)DesignInfoinline
getFFSRType(DesignCellType typeA)DesignInfoinlinestatic
getNet(std::string &tmpName)DesignInfoinline
getNets()DesignInfoinline
getNumCells()DesignInfoinline
getNumNets()DesignInfoinline
getPins()DesignInfoinline
getPredefinedClusters()DesignInfoinline
getType2Cells()DesignInfoinline
isBRAM(DesignCellType cellType)DesignInfoinlinestatic
isCarry(DesignCellType cellType)DesignInfoinlinestatic
isClockBuffer(DesignCellType cellType)DesignInfoinline
isDesignClock(DesignNet *tmpNet)DesignInfoinline
isDSP(DesignCellType cellType)DesignInfoinlinestatic
isFF(DesignCellType cellType)DesignInfoinlinestatic
isIO(DesignCellType cellType)DesignInfoinlinestatic
isLogicRelated(DesignCellType cellType)DesignInfoinline
isLUT(DesignCellType cellType)DesignInfoinlinestatic
isLUTRAM(DesignCellType cellType)DesignInfoinlinestatic
isMux(DesignCellType cellType)DesignInfoinlinestatic
isShifter(DesignCellType cellType)DesignInfoinline
JSONCfgDesignInfoprivate
loadClocks(std::string clockFileName)DesignInfo
loadUserDefinedClusterNets()DesignInfo
LUTFFDeterminedOccupationDesignInfoprivate
name2CellDesignInfoprivate
name2NetDesignInfoprivate
netlistDesignInfoprivate
pinsDesignInfoprivate
PinType_CLK enum valueDesignInfo
PinType_D enum valueDesignInfo
PinType_E enum valueDesignInfo
PinType_LUTInput enum valueDesignInfo
PinType_LUTOutput enum valueDesignInfo
PinType_Others enum valueDesignInfo
PinType_Q enum valueDesignInfo
PinType_SR enum valueDesignInfo
predefinedClustersDesignInfoprivate
printStat(bool verbose=false)DesignInfo
resetLUTFFDeterminedOccupation()DesignInfoinline
resetNetEnhanceRatio()DesignInfoinline
setDeterminedOccupation(int cellId, int occupation)DesignInfoinline
type2CellsDesignInfoprivate
updateFFControlSets()DesignInfo
~DesignInfo()DesignInfoinline