AMF-Placer  2.0
An Open-Source Timing-driven Analytical Mixed-size FPGA Placer
ParallelCLBPacker::PackingCLBSite Member List

This is the complete list of members for ParallelCLBPacker::PackingCLBSite, including all inherited members.

addCarry()ParallelCLBPacker::PackingCLBSiteinline
addLUTRAMMacro()ParallelCLBPacker::PackingCLBSiteinline
best_DirectConnectParallelCLBPacker::PackingCLBSiteprivate
best_mappedCellsParallelCLBPacker::PackingCLBSiteprivate
best_mappedFFsParallelCLBPacker::PackingCLBSiteprivate
best_mappedLUTsParallelCLBPacker::PackingCLBSiteprivate
best_SlotMappingParallelCLBPacker::PackingCLBSiteprivate
carryCellParallelCLBPacker::PackingCLBSiteprivate
CARRYChainParallelCLBPacker::PackingCLBSiteprivate
CARRYChainSiteOffsetParallelCLBPacker::PackingCLBSiteprivate
checkDirectLUTFFConnect(std::map< DesignInfo::DesignCell *, DesignInfo::DesignCell * > &FF2LUT, DesignInfo::DesignCell *tmpLUT, DesignInfo::DesignCell *tmpFF)ParallelCLBPacker::PackingCLBSiteinline
checkDirectLUTFFConnect_slack(std::map< DesignInfo::DesignCell *, DesignInfo::DesignCell * > &FF2LUT, DesignInfo::DesignCell *tmpLUT, DesignInfo::DesignCell *tmpFF)ParallelCLBPacker::PackingCLBSiteinline
checkIsCarrySite()ParallelCLBPacker::PackingCLBSiteinline
checkIsLUTRAMSite()ParallelCLBPacker::PackingCLBSiteinline
checkIsMuxSite()ParallelCLBPacker::PackingCLBSiteinline
checkIsNonCLBSite()ParallelCLBPacker::PackingCLBSiteinline
checkIsPrePackedSite()ParallelCLBPacker::PackingCLBSiteinline
CLBSiteParallelCLBPacker::PackingCLBSiteprivate
clockRegionAwareParallelCLBPacker::PackingCLBSiteprivate
compatibleInOneHalfCLB(int halfCLB, int anotherHalfCLB)ParallelCLBPacker::PackingCLBSiteinline
conflictLUTsParallelCLBPacker::PackingCLBSiteprivate
conflictLUTsContain(DesignInfo::DesignCell *tmpCell)ParallelCLBPacker::PackingCLBSiteinline
curDParallelCLBPacker::PackingCLBSiteprivate
debugParallelCLBPacker::PackingCLBSiteprivate
deltaDParallelCLBPacker::PackingCLBSiteprivate
determinedClusterInSiteParallelCLBPacker::PackingCLBSiteprivate
detScoreParallelCLBPacker::PackingCLBSiteprivate
finalMapToSlots()ParallelCLBPacker::PackingCLBSiteinline
finalMapToSlotsForCarrySite(int FFControlSetOrderId)ParallelCLBPacker::PackingCLBSite
finalMapToSlotsForCarrySite()ParallelCLBPacker::PackingCLBSite
finalMapToSlotsForCommonLUTFFInSite(int FFControlSetOrderId)ParallelCLBPacker::PackingCLBSite
finalMapToSlotsForCommonLUTFFInSite()ParallelCLBPacker::PackingCLBSite
findMuxFromHalfCLB(PlacementInfo::PlacementMacro *MUXF8Macro)ParallelCLBPacker::PackingCLBSite
findNeiborPUsFromBinGrid(DesignInfo::DesignCellType curCellType, float targetX, float targetY, float displacementLowerbound, float displacementUpperbound, int PUNumThreshold, const std::vector< PackingCLBSite * > &PUId2PackingCLBSite, float y2xRatio, std::set< PlacementInfo::PlacementUnit *, Packing_PUcompare > *res=nullptr, bool clockRegionAware=true)ParallelCLBPacker::PackingCLBSite
findNewClustersWithNeighborPUs()ParallelCLBPacker::PackingCLBSite
fixedLUTsInPairsParallelCLBPacker::PackingCLBSiteprivate
fixedPairedLUTsParallelCLBPacker::PackingCLBSiteprivate
getCarryCell()ParallelCLBPacker::PackingCLBSiteinline
getCarryMacro()ParallelCLBPacker::PackingCLBSiteinline
getCarrySiteOffset()ParallelCLBPacker::PackingCLBSiteinline
getCLBSite()ParallelCLBPacker::PackingCLBSiteinline
getConflictLUTs()ParallelCLBPacker::PackingCLBSiteinline
getDeterminedClusterInSite()ParallelCLBPacker::PackingCLBSiteinline
getDetScore()ParallelCLBPacker::PackingCLBSiteinline
getFFSlot(DesignInfo::DesignCell *targetCell)ParallelCLBPacker::PackingCLBSiteinline
getFixedPairedLUTs()ParallelCLBPacker::PackingCLBSiteinline
getHPWLChangeForPU(PlacementInfo::PlacementUnit *tmpPU)ParallelCLBPacker::PackingCLBSiteinline
getLUTRAMMacro()ParallelCLBPacker::PackingCLBSiteinline
getLUTSlot(DesignInfo::DesignCell *targetCell)ParallelCLBPacker::PackingCLBSiteinline
getNeighborPUs()ParallelCLBPacker::PackingCLBSiteinline
getNonCLBCell()ParallelCLBPacker::PackingCLBSiteinline
getPairPinNum(DesignInfo::DesignCell *LUTA, DesignInfo::DesignCell *LUTB)ParallelCLBPacker::PackingCLBSiteinline
getPlacementInfo() constParallelCLBPacker::PackingCLBSiteinline
getPriorityQueueTop()ParallelCLBPacker::PackingCLBSiteinline
getSlotMapping() constParallelCLBPacker::PackingCLBSiteinline
getSlotMappingRef()ParallelCLBPacker::PackingCLBSiteinline
getY2xRatio() constParallelCLBPacker::PackingCLBSiteinline
greedyMapMuxForCommonLUTFFInSite(int FFControlSetOrderId)ParallelCLBPacker::PackingCLBSite
greedyMapMuxForCommonLUTFFInSite()ParallelCLBPacker::PackingCLBSite
hasValidPQTop()ParallelCLBPacker::PackingCLBSiteinline
HPWLWeightParallelCLBPacker::PackingCLBSiteprivate
isCarryMacro(DesignInfo::DesignCell *cell)ParallelCLBPacker::PackingCLBSiteinline
isCarrySiteParallelCLBPacker::PackingCLBSiteprivate
isLUTRAMSiteParallelCLBPacker::PackingCLBSiteprivate
isMuxMacro(DesignInfo::DesignCell *cell)ParallelCLBPacker::PackingCLBSiteinline
isNonCLBSiteParallelCLBPacker::PackingCLBSiteprivate
isPQTopCompletelyAccptedByCells()ParallelCLBPacker::PackingCLBSiteinline
LUTRAMMacroParallelCLBPacker::PackingCLBSiteprivate
mapCarryRelatedCellsToSlots(PlacementInfo::PlacementMacro *_CARRYChain, float siteOffset)ParallelCLBPacker::PackingCLBSite
mapLUTRAMRelatedCellsToSlots(PlacementInfo::PlacementMacro *_LUTRAMMacro)ParallelCLBPacker::PackingCLBSite
mapMuxF7Macro(int halfCLBOffset, PlacementInfo::PlacementMacro *MUXF7Macro)ParallelCLBPacker::PackingCLBSite
mapMuxF8Macro(int muxF8Offset, PlacementInfo::PlacementMacro *MUXF8Macro)ParallelCLBPacker::PackingCLBSite
mappedCellsParallelCLBPacker::PackingCLBSiteprivate
mappedFFsParallelCLBPacker::PackingCLBSiteprivate
mappedLUTsParallelCLBPacker::PackingCLBSiteprivate
maxDParallelCLBPacker::PackingCLBSiteprivate
moveLUTToLUT6Slot()ParallelCLBPacker::PackingCLBSite
neighborPUsParallelCLBPacker::PackingCLBSiteprivate
nonCLBCellParallelCLBPacker::PackingCLBSiteprivate
numNeighborParallelCLBPacker::PackingCLBSiteprivate
PackingCLBSite(PlacementInfo *placementInfo, DeviceInfo::DeviceSite *CLBSite, int unchangedIterationThr, int numNeighbor, float deltaD, float curD, float maxD, unsigned int PQSize, float y2xRatio, float HPWLWeight, std::vector< PackingCLBSite * > &PUId2PackingCLBSite)ParallelCLBPacker::PackingCLBSiteinline
placementInfoParallelCLBPacker::PackingCLBSiteprivate
PQSizeParallelCLBPacker::PackingCLBSiteprivate
priorityQueueParallelCLBPacker::PackingCLBSiteprivate
PU2TopCntParallelCLBPacker::PackingCLBSiteprivate
PUId2PackingCLBSiteParallelCLBPacker::PackingCLBSiteprivate
refreshPrioryQueue()ParallelCLBPacker::PackingCLBSite
removeClustersIncompatibleWithDetClusterFromPQ()ParallelCLBPacker::PackingCLBSite
removeInvalidClustersFromPQ()ParallelCLBPacker::PackingCLBSite
removeInvalidPUsFromNeighborPUs()ParallelCLBPacker::PackingCLBSite
seedClustersParallelCLBPacker::PackingCLBSiteprivate
setClockRegionAwareTo(bool _clockRegionAware)ParallelCLBPacker::PackingCLBSiteinline
setDebug()ParallelCLBPacker::PackingCLBSiteinline
setDeterminedClusterInSite(PackingCLBCluster *tmpCluster)ParallelCLBPacker::PackingCLBSiteinline
setNonCLBCell(DesignInfo::DesignCell *_NonCLBCell)ParallelCLBPacker::PackingCLBSiteinline
slotMappingParallelCLBPacker::PackingCLBSiteprivate
unchangedIterationThrParallelCLBPacker::PackingCLBSiteprivate
unchangeIterationCntParallelCLBPacker::PackingCLBSiteprivate
updateConsistentPUsInTop()ParallelCLBPacker::PackingCLBSite
updateStep(bool initial, bool debug=false)ParallelCLBPacker::PackingCLBSite
y2xRatioParallelCLBPacker::PackingCLBSiteprivate
~PackingCLBSite()ParallelCLBPacker::PackingCLBSiteinline